Charudatta
Korde

Researcher Engineer Educator

Researching resource-efficient artificial intelligence and hardware acceleration — building open-source tools for AI, security, education and knowledge systems.

Research

Resource-efficient AI on edge hardware

Doctoral research (NIT Goa) on hardware acceleration of Generative Adversarial Networks for FPGA-based edge devices — evolutionary and multifractal methods to stabilise training, and hardware-aware design for low-latency, low-power inference.

92.05%
latency reduction · MFDFA GAN
86.03%
power reduction · MFDFA GAN
85%
FID improvement · 2D-MFDFA GAN
138 µs
inference latency @ Kintex-7 (vs 570 µs)

MFDFA-Enhanced GAN

Multifractal Detrended Fluctuation Analysis embedded in the discriminator for stable, hardware-optimised synthetic image generation — without changing the core GAN architecture.

−92.05% latency −86.03% power
GAN MFDFA FPGA Edge AI

Evolutionary-Enhanced GAN

Genetic-algorithm-optimised generator with wavelet-based discrimination, synthesised on the AMD Kintex-7 KC705 with the lowest area footprint among compared implementations.

138 µs vs 570 µs 24 mW vs 47 mW
GAN Wavelet FPGA Edge AI

2D-MFDFA GAN

A 2D multifractal discriminator for fast synthetic-data generation, deployed on the Kintex-7 KC705 through the NNGen framework with verified hardware results.

+85% FID 94% faster −81% power
MFDFA GAN NNGen FPGA
Research → code

From publication to implementation

Research and software are treated as one pipeline. Each paper is linked to its method, implementation and (where it exists) source code.

Research problem
GAN instability on edge hardware
Method
evolutionary · wavelet · MFDFA
Implementation
PyTorch · Python · HDL
Results
latency · power · FID
Publication
IEEE Access · iSES · INDICON
Source code
open research repos

Some publications have no public code yet — those are listed as paper-only rather than inventing links. Verified implementations are shown with their exact repository.

Projects

Projects

Open-source tools, research implementations and degree projects from the charudatta10 profile — every card links to its exact repository or live site, no generic profile links.

Flagship · pinned

orbit

A ~160-line minimalist LLM framework for Lua. Zero dependencies, zero vendor lock-in; agents, workflows and RAG in one file.

Lua LLM Agents
Flagship · pinned

forensic-fathers-library

Static site with a client-only RAG chatbot over the founding figures of forensic science — WebLLM in the browser, no server, no API keys.

HTML RAG WebLLM
Notable · pinned

license · MPLS

A composable, SPDX-compatible licensing framework — modular legal clauses instead of rewriting licenses, with monetisation built in.

Python Licensing Open source
Knowledge · pinned

link-net

Aggregated link hub — a curated, categorised collection of useful resources with custom link icons and fast setup.

Python Flask Jinja2
Automation

task-runner-SDLC

Automates init, deploy, licence, readme and maintenance tasks across projects (now maintained as PowerShell modules).

AI tooling

ai-orb · ai-rag · ai-translate

Agent framework, retrieval-augmented generation and code translation, each running on local models.

Security

one-time-share · sandLua

Secure single-download file sharing, and a Lua reverse-engineering sandbox with static and dynamic analysis.

Knowledge

wiki-notes · ibrain

Foam + Raito personal knowledge graph, and a Docsify-powered notes & wiki site.

Research · academic

Devanagari Recognizer

Handwritten Devanagari script recognition system from the Bachelor's project (2015) — the same line of work as the ISVLSI publication on FPGA pre-processing.

MATLAB OCR ML
Research

PGAN-DNN

2019 GAN research implementation (perceptual adversarial training experiments) — part of the doctoral exploration into stable GAN training that led to the INDICON publication.

PyTorch GAN Research
Education · 2015

Devanagari Script Recognition (Bachelor's)

Machine learning-based character recognition system with FPGA pre-processing (GEC Goa). Published at ISVLSI.

Education · 2017

TEC as Seismic Precursor (Master's)

MFDFA-based ionospheric pattern analysis for earthquake detection (GEC Goa & IIT Bombay). Presented at IAMG.

Education · 2019

Hybrid Evolutionary Optimization of GANs (PhD Work)

Evolutionary + backprop training framework for improved GAN convergence (NIT Goa). Published at INDICON.

Publications

Publications

Every entry verified against ORCID and Crossref. DOIs resolve to the publisher; the two conference papers without DOIs link to their ORCID records.

  • 2026

    MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation

    C. G. Korde, K. G. Shreeharsha, R. K. Siddharth, M. H. Vasantha, Y. B. Nithin Kumar

    IEEE Access  vol. 14, pp. 46700–46713 · −92.05% latency, −86.03% power

  • 2025

    Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation

    C. G. Korde, K. G. Shreeharsha, R. K. Siddharth, M. H. Vasantha, Y. B. Nithin Kumar

    IEEE Access  vol. 13, pp. 209009–209022 · 138 µs vs 570 µs, 24 mW vs 47 mW

  • 2025

    Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks

    C. G. Korde, K. G. Shreeharsha, R. K. Siddharth, M. H. Vasantha, Y. B. Nithin Kumar

    IEEE Access  vol. 13, pp. 150794–150805 · 85% FID gain, 94% faster, −81% power

  • 2024

    An Exponential Variation Based PSO for Analog Circuit Sizing in Constrained Environment

    K. G. Shreeharsha, R. K. Siddharth, C. G. Korde, M. H. Vasantha, Y. B. Nithin Kumar

    AEU — Int. J. Electron. Commun.  vol. 187, art. 155531

  • 2021

    Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm

    K. G. Shreeharsha, C. G. Korde, M. H. Vasantha, Y. B. Nithin Kumar

    IEEE iSES  pp. 127–130 · ~5× fewer iterations to plausible MNIST images

  • 2019

    Training of Generative Adversarial Networks with Hybrid Evolutionary Optimization Technique

    C. G. Korde, K. Manikantta Reddy, M. H. Vasantha, Y. B. Nithin Kumar

    IEEE INDICON  pp. 1–4

  • 2018

    FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics

    S. Barve, S. Raveendran, C. Korde, T. Panigrahi, Y. B. Nithin Kumar, M. H. Vasantha

    IEEE iSES  pp. 6–10

  • 2017

    Multifractal Analysis of Ionospheric Disturbances Triggered by Earthquakes

    C. G. Korde (IAMG Conference paper)

    IAMG Conference  paper-only · no DOI

  • 2015

    Implementation of FPGA Based Pre-Processing Algorithms for Devnagri Script Recognition System

    C. G. Korde (ISVLSI Conference paper)

    IEEE ISVLSI  paper-only · no DOI

ORCID · Google Scholar · Scopus · Web of Science

Now

What I'm working on now

A snapshot of current focus — research, learning and building.

Research

  • Wavelet- and evolutionary-based GAN discriminator improvements for training stability
  • Hardware-aware neural architecture refinements for edge deployment
  • Federated node synchronization protocols for distributed training

Building & learning

  • Rust blockchain prototype for DAO-driven educational governance
  • Torrent-based federated LLM training architecture
  • Advanced Rust, consensus algorithms and cryptoeconomic modeling

Long-term direction

Building decentralized AI infrastructure that integrates governance, distributed learning, and hardware-efficient optimization into a scalable open research ecosystem.

About

Researcher · Engineer · Educator

I build systems with logic, explore ideas with curiosity, and live with awareness. The concrete facts — education, experience, skills and achievements.

I am Charudatta Gurudas Korde — an engineer, developer, researcher, and educator driven by curiosity and depth. I think in systems. I build with intention. I research with discipline. And I teach to simplify complexity. My work lives at the intersection of architecture and abstraction — where ideas become structured systems and theory becomes implementation. I am drawn to decentralized technologies, open knowledge, and designing solutions that are minimal yet comprehensive.

Beyond engineering, I am a lifelong learner — anime, food, gardening, reading, and coding as a creative outlet. I value rest and reflection as much as productivity, and I believe technology should not only advance capability but also elevate awareness. Growth for me is holistic — intellectual, creative, and inner.

Academics

  • 2017 — 2026 (Expected)
    Ph.D. in VLSI & Reconfigurable Computing

    Research focus: hardware acceleration of GANs on FPGA-based edge devices. National Institute of Technology Goa.

  • 2015 — 2017 · 80%
    M.Tech. in Microelectronics

    Master's project: multifractal analysis of ionospheric TEC as a seismic precursor (GEC Goa & IIT Bombay).

  • 2011 — 2015 · 76%
    B.E. in Electrical & Electronics Engineering

    Bachelor's project: handwritten Devanagari script recognition with FPGA pre-processing (GEC Goa).

  • 2009 — 2011 · 72%
    Higher Secondary School Certificate (HSSC)
  • 1999 — 2009 · 69%
    Secondary School Certificate (SSC)

Experience

  • 2024 — Present
    Contract Lecturer, National Forensic Sciences University

    Teaching Incident Response and Vulnerability Assessment & Penetration Testing (VAPT), integrating applied cybersecurity practice with system-level analysis and research-informed instruction.

  • 2024
    Visiting Faculty, Goa Polytechnic College

    Laboratory instruction in Basic Electronics — circuit fundamentals, measurement techniques and applied engineering principles.

  • 2018 — Present
    Research Scholar, National Institute of Technology Goa

    Doctoral research in FPGA-based AI acceleration — GAN architectures, hardware-software co-design, and resource-efficient intelligent systems. Academic mentoring and laboratory guidance as Teaching Assistant.

  • 2019
    Software Validation Engineer, Intel

    Validated Quartus tool flows, contributing to verification processes, workflow robustness and software quality assurance.

  • 2015 — Present
    Independent Research & Open-Source Development

    Analytical and software development projects spanning medical signal analysis, data-intensive systems and automation tooling; open-source utilities for documentation generation, file-system organization and programmatic graphics.

Tools and disciplines

Core expertise
Python FPGA Design GAN Architectures Edge AI Distributed Systems Blockchain (P2P)
Programming & hardware
Verilog VHDL C CUDA MATLAB LaTeX
AI / ML stack
PyTorch TensorFlow NumPy Scikit-Learn Stable Diffusion LLM Integration
Security & systems
Malware Analysis VAPT Incident Response Cryptography Secure Architectures

Achievements & mentorship

  • Guided 6 postgraduate students in thesis writing — mentored research scholars across problem formulation, experimental design, system implementation and academic structuring in AI, GAN optimization and hardware-accelerated architectures.
  • Cleared Stage 1 — AI Grand Challenge — qualified in the initial evaluation round of the national-level AI Grand Challenge (PS12, Underwater Acoustic Systems).
  • Completed a 5K marathon — discipline, endurance and long-term consistency, applied to sustained research and systems engineering.
  • Poster presentation on edge computing optimization — clarity of communication across technical and non-technical audiences.
  • State-level chess tournament competitor — strategic reasoning, foresight and pattern recognition transferable to AI modeling and distributed systems design.
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