Researcher, engineer and educator
I research resource-efficient artificial intelligence, with a focus on generative models accelerated on FPGA-based edge hardware. I also teach cybersecurity and build open-source tools for AI, security and knowledge management.
Ph.D. candidate at NIT Goa. Contract Lecturer at the National Forensic Sciences University.
My doctoral research at NIT Goa investigates hardware acceleration of generative adversarial networks (GANs) on FPGA-based edge devices. It combines evolutionary and multifractal methods, which stabilise training, with hardware-aware design that lowers latency and power.
Embeds multifractal detrended fluctuation analysis in the discriminator. Training is more stable and the hardware implementation more efficient, without changing the core GAN architecture.
Latency reduced by 92.05% and power by 86.03%.
A genetic-algorithm-optimised generator paired with a wavelet-based discriminator. Synthesised on the AMD Kintex-7 KC705, it has the smallest area footprint among the implementations compared.
Latency of 138 µs against 570 µs, and 24 mW against 47 mW.
A two-dimensional multifractal discriminator for fast synthetic data generation, deployed on the Kintex-7 KC705 through the NNGen framework, with results verified on hardware.
FID improved by 85%, with 94% faster generation and 81% lower power.
My longer-term aim is open, decentralised AI infrastructure that combines governance, distributed learning and hardware-efficient optimisation.
Peer-reviewed journal and conference papers, most recent first.
MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation
C. G. Korde, K. G. Shreeharsha, R. K. Siddharth, M. H. Vasantha, Y. B. Nithin Kumar
IEEE Access, vol. 14, pp. 46700–46713. DOI
Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation
C. G. Korde, K. G. Shreeharsha, R. K. Siddharth, M. H. Vasantha, Y. B. Nithin Kumar
IEEE Access, vol. 13, pp. 209009–209022. DOI
Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks
C. G. Korde, K. G. Shreeharsha, R. K. Siddharth, M. H. Vasantha, Y. B. Nithin Kumar
IEEE Access, vol. 13, pp. 150794–150805. DOI
An Exponential Variation Based PSO for Analog Circuit Sizing in Constrained Environment
K. G. Shreeharsha, R. K. Siddharth, C. G. Korde, M. H. Vasantha, Y. B. Nithin Kumar
AEU — International Journal of Electronics and Communications, vol. 187, art. 155531. DOI
Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm
K. G. Shreeharsha, C. G. Korde, M. H. Vasantha, Y. B. Nithin Kumar
IEEE iSES, pp. 127–130. DOI
Training of Generative Adversarial Networks with Hybrid Evolutionary Optimization Technique
C. G. Korde, K. Manikantta Reddy, M. H. Vasantha, Y. B. Nithin Kumar
IEEE INDICON, pp. 1–4. DOI
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics
S. Barve, S. Raveendran, C. Korde, T. Panigrahi, Y. B. Nithin Kumar, M. H. Vasantha
IEEE iSES, pp. 6–10. DOI
Multifractal Analysis of Ionospheric Disturbances Triggered by Earthquakes
C. G. Korde
IAMG conference. No DOI; see the ORCID record.
Implementation of FPGA Based Pre-Processing Algorithms for Devnagri Script Recognition System
C. G. Korde
IEEE ISVLSI. No DOI; see the ORCID record.
Full record: ORCID Google Scholar Scopus Web of Science
Open-source software for AI, security, education and knowledge management. Each entry links to its own repository or site.
A minimalist LLM framework for Lua in roughly 160 lines. It has no dependencies or vendor lock-in, and supports agents, workflows and retrieval-augmented generation.
A static site with a chatbot on the founders of forensic science. Retrieval and generation run entirely in the browser with WebLLM, so there is no server and no API key.
A composable, SPDX-compatible licensing framework that assembles modular legal clauses, with monetisation options built in.
A curated, categorised hub of useful links, with custom icons and a quick setup.
task-runner-SDLC
Automates project initialisation, deployment, licensing, README generation and maintenance, now as PowerShell modules.
ai-orb, ai-rag and ai-translate
An agent framework, retrieval-augmented generation and code translation, each running on local models.
ai-doc-gen, ai-igen and ai_chat
Project documentation written by a local LLM, local illustration generation, and a lightweight chat interface.
one-time-share and sandLua
Secure single-download file sharing, and a Lua reverse-engineering sandbox with static and dynamic analysis.
wiki-notes and ibrain
A personal knowledge graph built with Foam and Raito, and a Docsify notes and wiki site.
project-tile, pypwa and file-tagger
Project showcase tiles, single-file PWA packaging for Python scripts, and tag-based file organisation.
devanagari-handwriting-recognizer
Handwritten Devanagari recognition from my 2015 bachelor's project, related to the ISVLSI paper on FPGA pre-processing.
PGAN-DNN
Perceptual adversarial training experiments from 2019, which preceded the INDICON paper on stable GAN training.
I am an engineer, researcher and educator working where hardware, machine learning and security meet. My research targets resource-efficient AI for edge systems, my teaching covers incident response and penetration testing, and my software favours small, dependency-light tools. I am especially interested in decentralised technology and open knowledge. Outside work I play chess, run, garden and read.
Ph.D., VLSI and Reconfigurable Computing
National Institute of Technology Goa. Hardware acceleration of GANs on FPGA-based edge devices.
M.Tech., Microelectronics
Thesis on multifractal analysis of ionospheric TEC as a seismic precursor, with GEC Goa and IIT Bombay.
B.E., Electrical and Electronics Engineering
Project on handwritten Devanagari recognition with FPGA pre-processing, at GEC Goa.
Contract Lecturer, National Forensic Sciences University (Dharwad Campus)
Teaches incident response and vulnerability assessment and penetration testing (VAPT), pairing hands-on practice with system-level analysis.
Visiting Faculty, Goa Polytechnic College
Led laboratory instruction in basic electronics, covering circuit fundamentals and measurement techniques.
Software Validation Engineer, Intel
Validated Quartus tool flows and contributed to verification processes and software quality assurance.
Research Scholar and Teaching Assistant, National Institute of Technology Goa
Doctoral research on FPGA-based AI acceleration and hardware-software co-design, alongside laboratory guidance and mentoring.
Independent research and open-source development
Projects in medical signal analysis, data-intensive systems and automation, plus open-source tools for documentation, file organisation and programmatic graphics.
Articles on developer tooling and digital note-taking, published on dev.to.
I welcome enquiries about research collaboration, hardware-accelerated machine learning, security education and mentoring.
charudatta.korde@nfsu.edu.in